A DRAM memory conventionally comprises a set of memory points (i.e., memory cells) arranged in a matrix of rows and columns of memory points between word lines and bit lines. Each memory point comprises an access transistor for a DRAM capacitor. The access transistor has a control electrode linked to a word line, a drain linked to a bit liner and a source linked to the DRAM capacitor.
A set of differential read/write amplifiers, generally denoted by the term sense amplifiers, ensures detection of a potential difference between two complementary bit lines BLT and BLC. Selection gateways selectively ensure the transfer of data between each local bit line, and one or more global bit lines or read and write lines.
Various architectures may be used to transfer information between the bit lines and the global bit lines (i.e., read and write lines). A single selection gateway may be used for each differential amplifier. This approach is accompanied by an increased density of components since each selection gateway generally comprises two transistors. Furthermore, the operation of reading such a memory is relatively lengthy. This type of memory does not allow early writing, so that the duration of a write cycle is relatively slow.
To alleviate the problem of slowness of the reading operation, another approach is based on using read/write circuits that are more complete. Each read/write amplifier can be supplemented with a set of transistors for managing the read/write operations on the global bit lines. These additional management transistors are typically eight in number.
Such an architecture enables the read and write operations to be made faster. However, each of the read and write stages must be linked to each read and write line BLT or BLC. Furthermore, the read stage suffers from a major drawback since it comprises MOS transistors placed in series, thereby limiting the current transferred and tending to slow down the memory read operation. Finally, the presence of eight transistors for each differential amplifier increases the overall capacitance of each read/write line of the memory.